Thursday, 10 December 2015

IBPS SO (IT Officer) Exam : Computer Quiz 72


IBPS SO (IT Officer) Exam Mock Test Quiz on Computer Architecture & Organization

Q.1. Where does a computer add and compare data?
(a) Hard disk     
(b) Floppy disk
(c) CPU chip      
(d) Memory chip


Q.2. Which of the following registers is used to keep track of address of the memory location where the next instruction is located?
(a) Memory Address Register    
(b) Memory Data Register          
(c) Instruction Register
(d) Program Register

Q.3. Pipelining strategy is called implement
(a) instruction execution            
(b) instruction prefetch              
(c) instruction decoding              
(d) instruction manipulation

Q.4. When the RET instruction at the end of subroutine is executed,
(a) the information where the stack is initialized is transferred to the stack pointer
(b) the memory address of the RET instruction is transferred to the program counter
(c) two data bytes stored in the top two locations of the stack are transferred to the program counter
(d) two data bytes stored in the top two locations of the stack are transferred to the stack pointer

Q.5. What is meant by a dedicated computer?
(a) which is used by one person only     
(b) which is assigned to one and only one task
(c) which does one kind of software      
(d) which is meant for application software only

Q.6. The most common addressing techniques employed by a CPU is
(a) immediate  
(b) direct           
(c) indirect        
(d) register
(e) All of the above

Q.7. When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the
(a) stack pointer             
(b) accumulator             
(c) program counter      
(d) stack

Q.8. Interrupts which are initiated by an instruction are
(a) internal        
(b) external       
(c) hardware    
(d) software

Q.9. Memory access in RISC architecture is limited to instructions
(a) CALL and RET            
(b) PUSH and POP          
(c) STA and LDA              
(d) MOV and JMP

Q.10. MIMD stands for ______
(a) Multiple instruction multiple data   
(b) Multiple instruction memory data
(c) Memory instruction multiple data    
(d) Multiple information memory data

Q.11. The average time required to reach a storage location memory and obtain its contents is called
(a) Latency time             
(b) Access time               
(c) Turnaround time     
(d) Response time

Q.12. Memory unit accessed by content is called ______
(a) Read only memory  
(b) Programmable memory       
(c) Virtual Memory        
(d) Associative memory

Q.13. n bits in operation code imply that there are ______ possible distinct operators
(a) 2n   
(b) 2n   
(c) n/2
(d) n2

Q.14. A three input NOR gate gives logic high output only when____
(a) one input is high      
(b) one input is low       
(c) two input are low    
(d) all input are high

Q.15. The multiplicand register & multiplier register of a hardware circuit implementing booth’s algorithm have (11101) & (1100). The result shall be _____
(a) (812)10        
(b) (-12)10         
(c) (12)10           
(d) (-812)10

Q.16. PSW is saved in stack when there is a _____
(a) interrupt recognized             
(b) execution of RST instruction              
(c) Execution of CALL instruction             
(d) All of these

Q.17. In computers, subtraction is carried out generally by _____
(a) 1’s complement method      
(b) 2’s complement method     
(c) signed magnitude method   
(d) BCD subtraction method

Q.18. Cache memory works on the principle of ______
(a) Locality of data         
(b) Locality of memory
(c) Locality of reference              
(d) Locality of reference & memory

Q.19. When CPU is executing a program that is part of the Operating system, it is said to be in _____
(a) Interrupt mode        
(b) System mode           
(c) Half mode   
(d) Simplex mode

Q.20. Register renaming is done in pipelined processors
(a) as an alternative to register allocation at compile time          
(b) for efficient access to function parameters and local variables
(c) to handle certain kinds of hazards
(d) as part of address

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